This invention relates to memory in semiconductor devices. More particularly, the present invention relates to fabricating memory cells and drive circuits on different layers of a semiconductor wafer for bipolar memory devices.
Nonvolatile memory solutions are a growing focus for the next generation of memory devices. Where floating-gate transistors satisfy many current commercial needs, expansion and improvement in the industry may require the next generation of memory storage to work with unipolar and bipolar memory types. Resistive random-access memory (RRAM), phase change memory (PCM), magnetoresistive random-access memory (MRAM), and other memory types present new challenges in integrating memory elements into current memory devices. In particular, finding a memory design that allows for greater memory cell densities on a semiconductor chip may provide for greater memory array efficiency and reliability.
A central problem associated with present memory devices is that peripheral circuitry provides a large area overhead on the semiconductor wafer, which results in less space available for the memory cell array. For example, past solutions for implementing more efficient memory device involved utilizing multiple semiconductor wafers to fashion the memory device or stack unipolar memory cells on top of each other. These solutions, however, regularly experience problems with significant wiring overhead due to pitch mismatches.